1. Field of the Invention
The present invention generally relates to memory devices, and more particularly, to a single ended sensing scheme for use in determining the data stored in memory cells of non-volatile memory circuits.
2. Description of Background of Art
An electrically erasable programmable read only memory ("EEPROM") is a non-volatile integrated memory circuit, which stores data in an array of memory cells formed on a silicon substrate and constructed from enhancement-type n-channel metal-oxide semiconductor field effect ("NMOS") transistors. Each memory cell consists of two NMOS transistors, a "select" transistor M.sub.s and a "memory" transistor M.sub.m, which are jointly organized into a memory array of aligned rows representing word lines and aligned columns representing bit lines. The word lines and bit lines are activated by a row decoder and a column decoder, respectively.
Typically, during the programming operation for the memory cell, a high voltage V.sub.pp of about 12 to 20 volts is transferred by the row decoder to the selected word line to turn "on" the select transistor of the selected memory cell. By the column decoder further transferring V.sub.pp to the selected bit line attached to the drain electrode of the select transistor, the memory transistor is placed in the "0" logic state with a threshold voltage ranging from approximately 0.8V to -2 volts.
During the erasure operation, the control gate of the selected memory cell is raised to a high voltage V.sub.pp and the bit line of the selected memory cell is lowered to 0 volts. Since the floating gate is electrically isolated from the memory transistor, once the high voltage V.sub.pp is removed, a charge remains on the floating gate and the threshold voltage of the memory transistor is raised to at least half of the overall power supply voltage V.sub.cc, which is approximately 1.5 to 6 volts. To detect whether the memory cell has been programmed or erased, a single ended sensing scheme is electrically coupled to each memory cell bit line. During the read mode, a read voltage of approximately V.sub.cc /2 is applied to the control gate of the memory transistor M.sub.m. This read voltage generally is greater than the threshold voltage of the memory transistor at the "0" logic state and less than the threshold voltage of the memory transistor at the "1" logic state. A ground control transistor M.sub.gc will pull the common source of the memory cells to ground.
When the read voltage is applied to the memory cell containing the programmed "0" logic state, that memory cell will lower the bit line voltage level. Alternatively, when a read voltage is applied to the memory cells containing the erased "1" logic state, the memory cell will not conduct because of a higher control gate threshold voltage and the input lead of the single ended sensing scheme will slightly increase the bit line voltage level. The single ended sensing scheme will then transform the corresponding logic state voltages into amplified output voltage V.sub.out levels.
Because memory products require a high density of memory cells to store as much data as possible, multiple memory cells in the same memory array are electrically coupled to the same bit line. This multiple usage of bit lines, however, results in the bit lines possessing a large loading capacitance, which increases the bit line voltage swing time between the low and the high voltage states. The relationship between the swing time and the swing voltage can be mathematically described by the following equation: EQU T=C.sub.bit V.sub.bit /I.sub.cell
where T is the time for the bit line to swing between the "0" and the "1" logic states; C.sub.bit is the bit line capacitance; V.sub.bit is the voltage swing of the bit line; and I.sub.cell is the current sinking into the memory cell. To reduce the time required to propagate data from a specific memory cell to the outside CMOS circuitry, a smaller voltage swing on the bit line is necessary. Unfortunately, in a high speed circuit environment the single ended sensing scheme with the small voltage swing is susceptible to bit line noise problems and voltage variations, which results in the generation of false data.
What is needed is a single input sensing scheme, which is more noise immune at high speeds, thereby enabling the sensing scheme to maintain optimal performance speeds and generate accurate data.